FIG. 1 shows an exemplary 1T1C (one-transistor, one capacitor) DRAM cell 100. This device includes a MOSFET pass-gate 102 and a storage capacitor 104 coupled therewith. The storage capacitor 104 uses either a trench technology or a stacked capacitor structure. The cell can be bulk-Si or Silicon on Insulator (SOI). This is currently the cell technology of choice for dense memory in both embedded and standalone applications. DRAM technology, however, inherently has a need for a non-negligible standby power supply due to the need to periodically refresh stored data. This is fundamental in a 1T1C cell since the current leakage of the pass-gate device in the DRAM cell is non-zero due to subthreshold, junction, and gate leakage currents.
As device dimensions are scaled, these currents inevitably increase due to short-channel effects, band-to-band tunneling, and gate oxide tunneling. Thus, especially in scaled technologies, standby power reduction in conventional DRAM is very difficult. With technology scaling, variability increases, which compounds these problems. In a large memory array, the refresh rate is limited by the cell with the lowest Vt (voltage) pass-gate while the performance is limited by the cell with the highest Vt pass-gate. With variability, the nominal device Vt must be very high to ensure that retention targets can be met. This requires very high channel doping, which, in turn, increases junction leakage and dopant-fluctuation-induced Vt variation.
Variability also means that the gate voltage (often charge-pumped to compensate for the Vt drop when the NFET pass-gate charges up the storage capacitor) on the pass-gate, such as word line (WL) high voltage, must be increased to maintain performance. This max voltage is now approaching fundamental limits in oxide breakdown characteristics.
Since VLSI technology is subject to power constraints, methods to reduce standby power are especially important. Reduced power benefits applications ranging from high performance (e.g. the amount of cache that can be added to a server is often limited by power dissipation) to low power (e.g. standby power for cellular phones determines battery life). Going forward, variability also limits DRAM scaling, which directly leads to tradeoffs in performance and/or power dissipation.
A mechanical memory cell has been proposed in the past, but this was targeted towards non-volatile memory applications and suffers from large cell size due to the need for multiple cantilever beams per cell. Single DRAM cell functionality based on mechanical actuation of carbon nanotubes has also been demonstrated, but the cell design is inadequate for efficient actuation of the cantilever beam (voltages of ˜15V were necessary) and relies upon un-established devices in the form of carbon nanotubes, which cannot be applied to, for example, conventional trench capacitor structures.